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TranslationMobile

集成電路片尺寸

"chip" in Chinese : n. (摔跤時(shí))用絆腿把對方摔倒的一種技巧。 vt. ( ...
"size" in Chinese : n. (用面粉、樹膠、樹脂等配制的)膠料，漿糊〔用于給紙 ...
"cog chip size package" in Chinese : 晶方尺寸構(gòu)裝
"csp chip size package" in Chinese : 芯片尺寸封裝
"chip" in Chinese : n. 1.碎片，削片，薄片；碎屑；薄木片；無價(jià)值的東西。 2.(陶器等的)缺 ...
"chip at" in Chinese : 拿取笑
"chip in" in Chinese : 插嘴, 捐助, 下賭注; 近擊入穴; 近穴擊入; 捐獻(xiàn)錢財(cái); 下注
"on chip" in Chinese : 片上; 片裝
"on-chip" in Chinese : 片上；芯片上
"by size" in Chinese : 按從小到大; 按大小; 依大小; 以體積分類
"for size" in Chinese : 為了試尺碼, 為了試試是否合適, 按不同尺碼
"in size" in Chinese : 在大小方面
"s size" in Chinese : 穿不下; 衛(wèi)生褲
"size" in Chinese : n. 1.大小，尺寸規(guī)模身材。 2.(鞋帽等的)尺碼，號(hào)；(紙張的)開。 3 ...
"size for" in Chinese : 為試尺碼

Examples

Ultrathin wafer level chip size package technology
超薄型圓片級芯片尺寸封裝技術(shù)
Ut - scsp ultra - thin - stacked chip size package
超薄疊層芯片尺寸封裝
Standard eia chip size available
標(biāo)準(zhǔn)eia貼片尺寸
Chip size limits
電路片尺寸限制
In terms of chip size , it s actually smaller than merced , and yet it s in the same process
在芯片大小方面，它實(shí)際上比merced小，而采用的是同樣的加工工藝。
This increase in chip size means that designs get more complicated because they must manipulate and hold larger systems called soc , or " system - on - chip " , designs
芯片尺寸的增加意味著設(shè)計(jì)工作將變得更加復(fù)雜，因?yàn)樗麄儽仨毑僮?、控制更大的系統(tǒng)（稱為soc或" system - on - chip "設(shè)計(jì)）。
Similar with design verification problem , to predigest chip level layout synthesis problem , the layout synthesis based on the standard - cell methodology can be divided into two levels : inner standard - cell and among standard - cells . however , along with the increasing of chip size , chip level layout synthesis problem become more complex if it still bases on general manual standard - cell . because the router cannot impose the characteristic of the transistors in the standard - cell , it may reduce the performance of the whole chip
通常，基于標(biāo)準(zhǔn)單元布圖模式將版圖綜合劃分成單元內(nèi)與單元間兩個(gè)層次，以簡化芯片級自動(dòng)版圖綜合問題的復(fù)雜性；但隨著芯片規(guī)模的不斷擴(kuò)大，基于主要以手工定制的小規(guī)模標(biāo)準(zhǔn)單元，芯片級版圖綜合問題的復(fù)雜性不斷增大，且標(biāo)準(zhǔn)單元間布線無法充分利用單元內(nèi)晶體管特征，影響芯片的整體性能。
According to process rules of the gaas mmic product line , we properly designed the circuit layout . in order to reduce the overall chip size , the transmission lines are folded with sufficient spacing to avoid interline coupling . the lange couplers are also folded to keep the 90 and 180 bits " sizes similar to other phase shift bits " sizes
結(jié)合實(shí)際mmic工藝線，合理設(shè)計(jì)移相器電路版圖，折疊微帶線并留出足夠大的線間距，以避免線間寄生耦合的發(fā)生，并折疊蘭格耦合器使90和180移相位的尺寸與其它相位的芯片尺寸保持一致。